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ISL54053
Data Sheet September 25, 2007 FN6460.2
Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch
The Intersil ISL54053 device is a low ON-resistance, low voltage, bidirectional, single pole/double throw (SPDT) analog switch designed to operate from a single +1.8V to +5.5V supply. Targeted applications include battery powered equipment which benefit from low rON (0.8) and fast switching speeds (tON = 24ns, tOFF = 10ns). The digital logic input is 1.8V logic compatible when using a single +3.0V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL54053 is offered in the 6 Ld 1.2mmx1.0mmx0.5mm TDFN package, alleviating board space limitations. The ISL54053 is a committed SPDT that consists of one normally open (NO) and one normally closed (NC) switch. This configuration can also be used as a 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE ISL54053 Number of Switches SW 1.8V rON 1.8V tON/tOFF 3V rON 3V tON/tOFF 5V rON 5V tON/tOFF Packages 1 SPDT or 2-1 MUX 2.3 68ns/45ns 1.1 29ns/12ns 0.8 24ns/10ns 6 Ld TDFN
Features
* Drop In replacement for the NLAS5123 * ON-resistance (rON) - VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 - VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 - VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 * rON matching between channels . . . . . . . . . . . . . . . . 0.004 * rON flatness (+4.5V supply) . . . . . . . . . . . . . . . . . . . . . 0.25 * Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V * Fast switching action (+4.5V supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns * Guaranteed break-before-make * ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV * 1.8V CMOS logic compatible (+3V supply) * Available in 6 Ld TDFN package * Pb-free (RoHS compliant)
Applications
* Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops * Portable test and measurement * Medical equipment * Audio and video switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Ordering Information
PART NUMBER (Note) ISL54053IRUZ-T* PART MARKING TEMP. RANGE (C) C -40 to +85 PACKAGE (Pb-Free) PKG. DWG. # 6 Ld (0.40mm pitch) 1.2x1.0x0.5 TDFN Tape and Reel L6.1.2x1.0A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54053 Pinout
(Note 1) ISL54053 (6 LD TDFN) TOP VIEW
NO GND NC 1 2 3 6 5 4 IN
Pin Descriptions
PIN V+ GND IN
V+ COM
FUNCTION System Power Supply Input (+1.8V to +5.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
COM NO NC
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
LOGIC 0 1 NOTE: PIN NC On Off PIN NO Off On
Logic "0" 0.5V. Logic "1" 1.4V with a 2.0V to 5.0V supply.
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FN6460.2 September 25, 2007
ISL54053
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 6 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+ VIN (Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+ Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON rON Matching Between Channels, rON rON Flatness, rFLAT(ON) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
Full V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 4.5V, ICOM = 100mA, VNO or VNC = 2.5V V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V, or floating 25 Full 25 Full 25 Full 25 Full 25 Full
0 -10 -150 -20 -300
0.86 1 0.004 0.004 0.25 0.27 5 9 -
V+ 10 150 20 300
V nA nA nA nA
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 5.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 3, Note 8) VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 600
25 Full 25 Full Full 25 25 25 25
-
24 30 10 15 10 26 80 -83 0.03
-
ns ns ns ns ns pC dB dB %
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FN6460.2 September 25, 2007
ISL54053
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS RL = 50 TEMP (C) 25 25 25 MIN (Notes 5, 6) TYP 190 16 48 MAX (Notes 5, 6) UNITS MHz pF pF
PARAMETER -3dB Bandwidth
NO or NC OFF Capacitance, COFF V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) V+ = 4.5V, f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+ Full 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ Full Full Full 2.4 -0.1 0.8 0.1 V V A 1.8 0.075 5.5 0.1 2.5 V A A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON rON Matching Between Channels, rON rON Flatness, rFLAT(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion -3dB Bandwidth
Full V+ = 3.0V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) V+ = 3.0V, ICOM = 100mA, VNO or VNC = 1.5V V+ = 3.0V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 7) 25 Full 25 Full 25 Full
0 -
1.1 0.004 0.33 -
V+ 1.2 1.5 0.14 0.14 0.35 0.4
V
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 3.6V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 8) VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 0.5VP-P, RL = 600 RL = 50 f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
25 Full 25 Full Full 25 25 25 25 25 25 25
-
29 35 12 17 10 32 80 -83 0.03 190 16 48
-
ns ns ns ns ns pC dB dB % MHz pF pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS
Full Full Full
1.4 -0.1
-
0.5 0.1
V V A
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FN6460.2 September 25, 2007
ISL54053
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Charge Injection, Q
Full V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+, (See Figure 5) 25 Full
0 -
2.33 2.54
V+ -
V
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 8) VG = 0, RG = 0, CL = 1.0nF (See Figure 2)
25 Full 25 Full Full 25
-
68 93 45 71 15 18
-
ns ns ns ns ns pC
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Limits established by characterization and are not production tested. Full Full 1 0.4 V V
Test Circuits and Waveforms
VINH LOGIC INPUT VINL tOFF SWITCH INPUT VNx 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO OR NC COM IN GND RL 50 CL 35pF VOUT 50% tr < 20ns tf < 20ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) --------------------------R L + r ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
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FN6460.2 September 25, 2007
ISL54053 Test Circuits and Waveforms (Continued)
V+ C
SWITCH OUTPUT VOUT
VOUT
RG VINH
NO OR NC
COM
VOUT
LOGIC INPUT
ON OFF
ON VINL VG GND IN CL LOGIC INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
VINH LOGIC INPUT VINL
NO VNX NC IN LOGIC INPUT GND RL 50 CL 35pF COM VOUT
SWITCH OUTPUT VOUT
90% 0V tD
CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME
V+ C SIGNAL GENERATOR rON = V1/100mA
NO OR NC NO OR NC
V+ C
VNX IN 0V OR V+
100mA V1 IN VINL OR VINH
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
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FN6460.2 September 25, 2007
ISL54053 Test Circuits and Waveforms (Continued)
V+ C V+ C
50
NO OR NC
COM
NO or NC
IN1 0V OR V+
SIGNAL GENERATOR
IN IMPEDANCE ANALYZER
COM
VINL OR VINH
ANALYZER RL
NC OR NO GND
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54053 is a bidirectional, single pole/double throw (SPDT) analog switch which offers precise switching capability from a single 1.8V to 5.5V supply with low ON-resistance (0.8) and high speed operation (tON = 24ns, tOFF = 10ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (5.5W), low leakage currents (300nA max) and the small TDFN package. The low on-resistance and rON flatness provide very low insertion loss and distortion to application that require signal reproduction.
purpose of using a low rON switch. Connecting schottky diodes to the signal pins (as shown in Figure 8) will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
INX VNX VCOM
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the
GND OPTIONAL SCHOTTKY DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54053 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4.5V maximum supply voltage, the ISL54053 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.8V but the part will operate with a supply below 1.8V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables starting on page 3 and "Typical Performance Curves" on page 8 for details.
FN6460.2 September 25, 2007
7
ISL54053
V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high off isolation and crosstalk rejection provided by this family. At 100kHz, off isolation is about 80dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 5V (see Figure 15). At 5V the VIH level is about 1.2V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
Leakage Considerations
ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
High-Frequency Performance
In 50 systems, the ISL54053 has a -3dB bandwidth of 190MHz (see Figure 16). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off isolation is
Typical Performance Curves TA = +25C, Unless Otherwise Specified.
2.5 ICOM = 100mA V+ = 1.8V 2.0 0.8 1.5 rON () rON () V+ = 2.7V 1.0 V+ = 3V 0.5 0.3 0 0 1 2 VCOM (V) 3 4 5 0.2 0 1 2 VCOM (V) 3 V+ = 4.5V V+ = 5V 0.7 +85C 0.6 0.5 0.4 +25C 0.9 1.0
-40C V+ = 5V ICOM = 100mA 4 5
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
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FN6460.2 September 25, 2007
ISL54053 Typical Performance Curves TA = +25C, Unless Otherwise Specified. (Continued)
1.5 1.4 1.3 1.2 rON () 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 0.5 1.0 1.5 VCOM (V) 2.0 -40C V+ = 3.0V ICOM = 100mA 2.5 3.0 +25C -40C 1.0 +85C rON () 2.0 +85C 1.5 +25C 2.5 3.0 V+ = 1.8V ICOM = 10mA
0.5 0 0.5 1.0 VCOM (V) 1.5 1.8
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
100 90 80 70 tOFF (ns) tON (ns) 60 50 40 30 20 10 0 1.8 2.8 -40C +85C +25C -40C
80
60
-40C
40
+25C
20 +85C
V+ (V)
3.8
4.8
0 1.8
-40C
2.8 V+ (V)
3.8
4.8
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
1.6 1.4 1.2 VINH 1.0 0.8 0.6 0.4 0.2 2.0 VINL
NORMALIZED GAIN (dB) 4.5 5.0 5.5
0 -1 -2 -3
GAIN
VINH AND VINL (V)
V+ = 5.0V RL = 50 VIN = 0.2VP-P to 2VP-P 2.5 3.0 3.5 4.0 V+ (V) 0.01k 0.1k 10M 1M FREQUENCY (Hz) 100M 1G
FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 16. FREQUENCY RESPONSE
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FN6460.2 September 25, 2007
ISL54053 Typical Performance Curves TA = +25C, Unless Otherwise Specified. (Continued)
0 V+ = 1.8V to 5.5V -20 -20 OFF ISOLATION (dB) 0 40 30 20 CROSSTALK (dB) -40 ISOLATION -60 CROSSTALK -40 10 0 Q (pC) -10 -20 -30 -40 -50 -120 1k 10k 100k 1M 10M FREQUENCY (Hz) -120 100M 500M -60 0 1 2 VCOM (V) 3 4 5 V+ = 1.8V V+ = 3.0V V+ = 5V V+ = 3.0V
-60
-80
-80
-100
-100
FIGURE 17. CROSSTALK AND OFF ISOLATION
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 57 PROCESS: Submicron CMOS
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FN6460.2 September 25, 2007
ISL54053 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E A B
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS
PIN 1 REFERENCE 2X 0.10 C 2X 0.10 C TOP VIEW DETAIL A 0.10 C
D
SYMBOL A A1 A3 b D
MIN 0.45 -
NOMINAL 0.50 0.127 REF
MAX 0.55 0.05
NOTES -
0.15 0.95 1.15
0.20 1.00 1.20 0.40 BSC
0.25 1.05 1.25
5 -
A 7X 0.08 C A1 A3 SIDE VIEW 4X e 1 L1 3 5X L C SEATING PLANE
E e L L1 N Ne NOTES:
0.30 0.40
0.35 0.45 6 3
0.40 0.50
2 3
DETAIL B
0
-
12
4 Rev. 2 8/06
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6 4 b 6X 0.10 C A B 0.05 C NOTE 3
2. N is the number of terminals. 3. Ne refers to the number of terminals on E side. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
0.1x45 CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255.
A1 DETAIL A
A3 DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
1.40 0.20 0.45 0.20 0.40 LAND PATTERN 10 0.30 0.35
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6460.2 September 25, 2007

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